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Difference between revisions of "NVGate DSP computation SPU"
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NVGate DSP computation SPU (view source)
Revision as of 17:01, 15 February 2022
, 17:01, 15 February 2022→Recorder
(→SOA) |
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| Line 62: | Line 62: | ||
| 51200 or upper || 1 || 0.66 | | 51200 or upper || 1 || 0.66 | ||
|- | |- | ||
| 32768 || 0.66 || 0. | | 32768 || 0.66 || 0.44 | ||
|- | |- | ||
| 25600 || 0.5 || 0.33 | | 25600 || 0.5 || 0.33 | ||
|- | |- | ||
| 16384 || 0.33 || 0. | | 16384 || 0.33 || 0.22 | ||
|- | |- | ||
| 12800 || 0.25 || 0. | | 12800 || 0.25 || 0.167 | ||
|- | |- | ||
| Else || 0.125 || 0. | | Else || 0.125 || 0.083 | ||
|} | |} | ||